Flash memories have been popularly used in nonvolatile semiconductor memory technology due to its non-volatility. Flash memories can be classified into two types, including stacked-gate structure and split-gate structure. A stacked-gate structure generally has an over-erase problem, which may increase the complexity of circuit design. Relatively speaking, a split-gate structure effectively avoids an over-erase effect and enables a simplified circuit design. Besides, in the split-gate structure, programming is performed by hot electron injection at a source, which enables higher programming efficiency. Therefore, flash memories with a split-gate structure are widely used in various electronic products, such as smart cards, Subscriber Identity Module (SIM) cards, microcontrollers or mobile phones.
In a flash memory with a split-gate structure, each split-gate flash memory unit includes a source, a drain, a first control gate, a word line gate and a second control gate. To each split-gate flash memory unit, the source and the drain are connected with corresponding bit lines respectively, the word line gate is connected with a word line, and the first and second control gates are connected with corresponding control gate lines respectively.
Operations to the flash memory unit with the split-gate structure include programming, reading and erasing. If the flash memory unit has the split-gate structure where each transistor includes two floating gates, when one of the two floating gates is to be programmed, a positive voltage is applied to the control gate line connected with the one floating fate, and a programming voltage is applied to the bit lines connected with the source and the drain, and to the word line and the control gate connected with the other floating gate which is not programmed. In this way, the one floating gate to be programmed is selected, a current required in the programming is ensured to go through, and electron energy conducted between the source and the drain is increased. When thermions are injected into the one floating gate to be programmed, the programming operation is completed. When a data reading operation is to be performed to the flash memory unit with the split-gate structure, a voltage is applied to the word line, and a current on the word line is read. If the current is relatively large, the read data is 1; or if the current is relatively small, the read data is 0. When no electron is stored in the floating gates, it indicates that the flash memory unit stores data of 1; or when electrons are stored in the floating gates, it indicates that the flash memory unit stores data of 0. When the voltage is applied to the word line, a voltage is also applied to the drain. A current is generated due to movement of a large amount of electrons between the source and the drain. By the bit line detecting the current between the source and the drain, how many electrons are stored in the floating gates is determined, so as to realize reading the data stored in the flash memory unit. When an erasing operation is to be performed to the flash memory unit with the split-gate structure, a positive voltage is applied to the source, and electrons injected into the floating gates are attracted to the source using a tunnel effect between the floating gates and the source, so that no electron is stored in the floating gates any more, that is, erasing is realized.
In existing flash memories with a split-gate structure, to save an area and simplify circuit design, generally, at least two split-gate memory units share a bit line and/or a word line and/or a control gate line.
FIG. 1 schematically illustrates a structural diagram of a flash memory unit with a split-gate structure.
Referring to FIG. 1, the flash memory unit includes a plurality of first split-gate flash memory units 100 and a plurality of second split-gate flash memory units 200. Each first split-gate flash memory unit 100 and each second split-gate flash memory unit 200 may include a source (not shown), a drain (not shown), a first control gate (not shown), a word line gate (not shown) and a second control gate (not shown), respectively. Besides, each first split-gate flash memory unit 100 and each second split-gate flash memory unit 200 includes a first storing bit A and a second storing bit B.
The source of the first split-gate flash memory unit 100 is connected with a first bit line BL0, the source of the second split-gate flash memory unit 200 is connected with a second bit line BL2, the drain of the first split-gate flash memory unit 100 is connected with the drain of the second split-gate flash memory unit 200 and a third bit line BL1, the first control gate of the first split-gate flash memory unit 100 is connected with the first control gate of the second split-gate flash memory unit 200 and a first control gate line CG0, the second control gate of the first split-gate flash memory unit 100 is connected with the second control gate of the second split-gate flash memory unit 200 and a second control gate line CG1, and the word line gate of the first split-gate flash memory unit 100 is connected with the word line gate of the second split-gate flash memory unit 200 and a word line WL.
Referring to FIG. 1, the flash memory unit includes the plurality of first split-gate flash memory units 100 and the plurality of second split-gate flash memory units 200. The plurality of first split-gate flash memory units 100 and the plurality of second split-gate flash memory units 200 share the word line WL, the first control gate line CG0 and the second control gate line CG1. A first pair of first split-gate flash memory unit 100 and second split-gate flash memory unit 200 share the bit line BL1, a second pair of first split-gate flash memory unit 100 and second split-gate flash memory unit 200 share the bit line BL4, an nth pair of first split-gate flash memory unit 100 and second split-gate flash memory unit 200 share the bit line BLk, and so on, which is not described in detail here.
When a reading and/or programming operation is performed to the flash memory unit with the split-gate structure in FIG. 1, for example, to the second storing bit B in the first split-gate flash memory unit 100, a potential difference between the second bit lint BL2 and the third bit line BL1 may result in an electric leakage to cause a leakage current therebetween, which may reduce efficiency and accuracy of the reading and/or programming operations to the second storing bit B in the first split-gate flash memory unit 100.
Therefore, there is a need to improve efficiency and accuracy of reading and programming operations to a flash memory unit.